1. Field of the Invention
The present invention relates to a memory integrated circuit package and a method of making the same, and more particularly to a lead-on chip type package to be used for packaging a memory integrated circuit of 16-mega grade or greater and a method of making the same.
2. Description of the Prior Art
FIG. 1 is a sectional view of a package construction of a general memory integrated circuit (IC). On the other hand, FIG. 2 is a plan view of a lead frame of the memory IC shown in FIG. 1. For making such a package construction, a lead frame is first prepared which is adapted to package a chip obtained by dicing a wafer. The lead frame is denoted by the reference numeral 13 in FIGS. 1 and 2. As shown in FIG. 2, the lead frame 13 comprises a paddle 13a to which a semiconductor chip 11 prepared by dicing a wafer is attached, a plurality of inner leads 13b electrically connected to the chip 11 inwardly of the package, a plurality of outer leads 13c electrically connected to other elements outwardly of the package, a pair of spaced side rails 13d adapted to maintain the shape of the lead frame 13, dam bars 13e adapted to support the inner and outer leads 13b and 13c such that they are uniformly spaced between the side rails 13d, a pair of support bars 13f adapted to support the paddle 13a between the side rails 13d, and a plurality of locking holes 13g.
Attaching the chip 11 to the paddle 13a of lead frame 13 is achieved by a die bonding that is carried out after the preparation of the lead frame 13 having the above-mentioned construction. Subsequently, a wire bonding is carried out for electrically connecting bonding pads 12 of the chip 11 to corresponding inner leads 13b by means of wires 14. The bonding pads 12 are formed on the surface of chip 11, so as to achieve the wire bonding as mentioned above. They are formed in a double line in case of a dual in line type package and in a single line in case of a single in line type package. The illustrated case corresponds to the dual in line type package.
The lead frame 13 which has been subjected to the die bonding and wire bonding is then positioned in, a mold 15 having a mold cavity corresponding a desired shape of a package to be produced. Thereafter, an epoxy molding compound (EMC) 16 is charged into the mold cavity of the mold 15 and a molding is then carried out to mold the semiconductor chip 11 and the inner leads 13b.
After molding, a trimming is carried out to remove dam bars 13e from the molded package. Subsequently, a forming process for shaping the outer leads 13c into a desired shape is performed. Thus, a memory IC package having the construction shown in FIG. 1 is obtained.
However, recent technical developments in manufacture of semiconductor elements lead memory ICs to be on an increasing trend in capacity. This trend also causes bare chips contained in semiconductor packages to increase in size. As a result, the occupied area of bare chip in the overall area of semiconductor package is on an increasing trend, resulting in an increase in the overall thickness of package.
Such an increase in the area occupied by the bear chip in the overall memory IC package area prevents the provision of a space assuring an accurate arrangement of the lead frame in the package. For solving this problem, there has been known a lead on chip (LOC) packaging technique wherein a packaging is achieved under the condition that a lead frame is laid on a chip.
Such a LOC packaging technique was used by IBM Corporation in U.S.A. in making 1-mega dynamic random access memories (1M DRAMs) and then by Hitachi, Ltd. in Japan in making 4M DRAMs. The LOC packaging technique will be a new packaging technique used in making 16M DRAM.
FIG. 3 is a sectional view of a construction of a conventional LOC package. As shown in FIG. 3, this LOC package comprises a semiconductor chip 31 attached to a paddle 34a of a lead frame and provided with a plurality of bonding pads 32 arranged in a line at the center portion of the upper surface of the semiconductor chip 31, an insulating film 33 formed over the upper surface of semiconductor chip 31 except for the surface portion corresponding to the bonding pads 32, that is, over both side portions of the upper surface of semiconductor chip 31, a plurality of inner leads 34b each extending such that its one end is positioned over the upper surface of semiconductor chip 31 attached to the paddle 34a of lead frame, each inner lead being electrically connected to each corresponding bonding pad 32 by means of a wire 35, a plurality of outer leads 34c each extending from the other end of each corresponding inner lead 34b and having a J shape, each outer lead being electrically connected to other external element, and a package body 36 surrounding the semiconductor chip 31, the insulating film 33 and the inner leads 34b.
Referring to FIG. 4, there is illustrated a construction of a lead frame for the conventional LOC package shown in FIG. 3. In similar to the construction of FIG. 2, the lead frame shown in FIG. 4 comprises a paddle 34a, a plurality of inner leads 34b, a plurality of outer leads 34c, a pair of side rails 34d, dam bars 34e, support bars 34f and locking holes 34g. In this case, however, each inner lead 34b has a sufficiently long length so that its one end can be positioned over the upper surface of the semiconductor chip 31 which is to be attached to the paddle 34a.
Now, a method of making such a LOC package having the above-mentioned construction will be described.
First, a lead frame 34 having the construction of FIG. 4 is prepared. Thereafter, the semiconductor chip 31 which was previously prepared by dicing a wafer is attached to the paddle 34a of the lead frame 34 using a die bonding. As the insulating film 33, a polyimide layer having a predetermined thickness is then coated over both side portions of the upper surface of semiconductor chip 31. A wire bonding is then carried out for electrically connecting the inner leads 34b to corresponding bonding pads of the chip 31, by means of wires 35.
Following the wire bonding, a molding is carried out for molding a predetermined part including the semiconductor chip 31, the insulating film 33 and the inner leads 34b, with an epoxy molding compound. That is, the lead frame 34 carrying the chip 31 is positioned in a mold (not shown). At this time, the outer leads 34c of lead frame 34 are positioned outwardly of the mold. The epoxy molding compound is charged into a mold cavity of the mold and the predetermined part is molded to form the package body 36.
A trimming is then performed for removing dam bars 34d and support bars 34f. Thereafter, a forming process for bending the outer leads 34c into a J-shape is carried out. Thus, a single in line type LOC package is obtained.
Such a LOC package has an advantage of increasing the area occupied by inner leads 34b in the package, in that the inner leads 34b of the lead frame 34 extend to an active cell of the semiconductor chip 31 and are electrically connected to the semiconductor chip 31 by means of the wires 35.
However, this type of LOC package requires the use of a polymer as a non-conductive material for insulating the semiconductor chip 31 from the inner leads 34b of lead frame 34. The polymer is provided between the semiconductor chip 31 and the inner leads 34b of lead frame 34. The use of polymer results in a problem of decreasing bonding forces between the polymer and the lead frame 34 and between the lead frame 34 and the package body 36 made of the epoxy molding compound. Moreover, there is another problem that undesirable parasitic capacitance may occur between each inner lead 34b of lead frame 34 and a circuit of the semiconductor chip 31 disposed beneath the inner lead 34b.
Such a parasitic capacitance caused by the wire bonding between the semi conductor chip 31 and each inner lead 34b of lead frame 34 extending to the upper surface of semiconductor chip 31 can be avoided by forming the polymer layer thick so that the semiconductor chip 31 is perfectly insulated from each inner lead 34b. However, the increased thickness of polymer layer causes the overall memory IC package to increase in thickness. As a result, it is impossible to produce laminated packages.